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features description SN65LVDS301 slls681c ? february 2006 ? revised august 2006 programmable 27-bit display serial interface transmitter fpc cabling typically interconnects the SN65LVDS301 with the display. compared to flatlink?3g serial interface technology parallel signaling, the lvds301 outputs significantly compatible with flatlink3g receivers such as reduce the emi of the interconnect by over 20 db. sn65lvds302 the electromagnetic emission of the device itself is very low and meets the meets sae j1752/3 input supports 24-bit rgb video mode 'm'-spec. (see figure 37 ) interface 24-bit rgb data, 3 control bits, 1 parity bit the SN65LVDS301 supports three power modes (shutdown, standby and active) to conserve power. and 2 reserved bits transmitted over 1, 2 or 3 when transmitting, the pll locks to the incoming differential lines pixel clock pclk and generates an internal sublvds differential voltage levels high-speed clock at the line rate of the data lines. effective data throughput up to 1755 mbps the parallel data are latched on the rising or falling edge of pclk as selected by the external control three operating modes to conserve power signal cpol. the serialized data is presented on the ? active-mode qvga 17.4 mw (typ) serial outputs d0, d1, d2 with a recreated pclk ? active-mode vga 28.8 mw (typ) generated from the internal high-speed clock, output ? shutdown mode ? 0.5 m a (typ) on the clk output. if pclk stops, the device enters a standby mode to conserve power ? standby mode ? 0.5 m a (typ) the parallel (cmos) input bus offers a bus-swap bus swap for increased pcb layout feature. the swap pin configures the input order of flexibility the pixel data to be either r[7:0]. g[7:0], b[7:0], vs, 1.8-v supply voltage hs, de or b[0:7]. g[0:7], r[0:7], vs, hs, de. this esd rating > 2 kv (hbm) gives a pcb designer the flexibility to better match the bus to the host controller pinout or to put the typical application: host-controller to transmitter device on the top side or the bottom side display-module interface of the pcb. pixel clock range of 4 mhz?65 mhz failsafe on all cmos inputs packaging: 80 pin 5mm 5mm m bga ? very low emi meets sae j1752/3 'm'-spec the SN65LVDS301 serializer device converts 27 parallel data inputs to 1, 2, or 3 sub low-voltage differential signaling (sublvds) serial outputs. it loads a shift register with 24 pixel bits and 3 control bits from the parallel cmos input interface. in addition to the 27 data bits, the device adds a parity bit and two reserved bits into a 30-bit data word. each word is latched into the device by the pixel clock (pclk). the parity bit (odd parity) allows a receiver to detect single bit errors. the serial shift register is uploaded at 30, 15, or 10 times the pixel-clock data rate depending on the number of serial links used. a copy of the pixel clock is output on a separate differential output. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. flatlink is a trademark of texas instruments. m bga is a registered trademark of tessera, inc.. production data information is current as of publication date. copyright ? 2006, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www.ti.com flatlink 3g ? 14 7 * 36 9 # 25 8 0 application processor with rgb video interface lvds302 lvds301 lcd driver data clk
description (continued) SN65LVDS301 slls681c ? february 2006 ? revised august 2006 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. two link select lines ls0 and ls1 control whether 1, 2 or 3 serial links are used. the txen input may be used to put the SN65LVDS301 in a shutdown mode. the SN65LVDS301 enters an active standby mode if the input clock pclk stops. this minimizes power consumption without the need for controlling an external pin. the SN65LVDS301 is characterized for operation over ambient air temperatures of ?40 c to 85 c. all cmos inputs offer failsafe features to protect them from damage during power-up and to avoid current flow into the device inputs during power-up. an input voltage of up to 2.165 v can be applied to all cmos inputs while v dd is between 0v and 1.65v. functional block diagram 2 submit documentation feedback www.ti.com [0..26] 0 1 pll multiplier txen pclk vs hs b[0:7] g[0:7] r[0:7] de ls1 88 8 sublvds d0+d0? sublvds d2+d2? sublvds clk+clk? sublvds d1+d1? ls0 cpol swap parity calc 1 0 ipclk bit28=0bit27=0 3x10, 2x15, or 1x30?bit parallel to serial conversion bit29 glitch supression control / standby monitor x1 x10, x15, or x30
pinout - top view swap pin functionality SN65LVDS301 slls681c ? february 2006 ? revised august 2006 the swap pin allows the pcb designer to reverse the rgb bus to minimize potential signal crossovers in the pcb routing. the two drawings beneath show the rgb signal pin assignment based on the swap-pin setting. figure 1. swap pin = 0 figure 2. swap pin = 1 3 submit documentation feedback www.ti.com 9 8 7 6 4 5 3 2 1 ad c b g f e h j g0 b7 r7 b0 de hs vs pclk b5 b1 b4 b2 b3 b6 r1 g6 g5 g3 g2 g1 r3 r6 r5 r2 r4 g7 r0 g4 SN65LVDS301 top view swap swap=0 9 8 7 6 4 5 3 2 1 ad c b g f e h j g7 r0 b0 r7 de hs vs pclk r2 r6 r3 r5 r4 r1 b6 g1 g2 g4 g5 g6 b4 b1 b2 b5 b3 g0 b7 g3 SN65LVDS301 top view swap swap=1 1.8v
SN65LVDS301 slls681c ? february 2006 ? revised august 2006 table 1. numeric pin list pin swap signal pin swap . . signal pin swap signal a1 ? gnd 0 b6 0 b1 c1 f1 0 g2 1 r1 1 r6 a2 1 g5 0 b7 0 b2 c2 f2 0 g4 1 r0 1 r5 a3 1 g3 c3 unpopulated f3 ? vdd 0 g6 c4 ? vdd f4 ? gnd a4 1 g1 c5 ? gnd f5 ? gnd 0 r0 c6 ? vdd f6 ? gnd a5 1 b7 c7 ? vdd f7 ? gnd 0 r2 c8 ? gnd f8 ? v ddplld a6 1 b5 c9 ? ls0 f9 ? d1+ 0 r4 0 b4 g1 ? pclk a7 d1 1 b3 1 r3 0 b0 g2 0 r6 0 b5 1 r7 a8 d2 1 b1 1 r2 g3 ? v dd a9 ? gnd d3 ? vdd g4 ? gnd 0 g0 d4 ? gnd g5 ? gnd b1 1 g7 d5 ? gnd g6 ? gnd 0 g1 d6 ? gnd g7 ? gnd b2 1 g6 d7 ? gnd g8 ? gnd lvds 0 g3 d8 ? ls1 g9 ? d1? b3 1 g4 d9 ? d2+ h1 ? hs 0 g5 0 b3 h2 ? vs b4 e1 1 g2 1 r4 h3 ? gnd 0 g7 e2 ? gnd h4 ? gnd lvds b5 1 g0 e3 ? vdd h5 ? v ddlvds 0 r1 e4 ? gnd h6 ? gnd plla b6 1 b6 e5 ? gnd h7 ? v ddplla 0 r3 e6 ? gnd h8 ? v ddlvds b7 1 b4 e7 ? gnd h9 ? cpol 0 r5 e8 ? gnd plld j1 ? gnd b8 1 b2 e9 ? d2? j2 ? de 0 r7 j3 ? txen b9 1 b0 j4 ? d0? j5 ? d0+ j6 ? clk? j7 ? clk+ j8 ? swap j9 ? gnd lvds 4 submit documentation feedback www.ti.com
SN65LVDS301 slls681c ? february 2006 ? revised august 2006 terminal functions name i/o description d0+, d0? sublvds data link (active during normal operation) sublvds data link (active during normal operation when ls0 = high and ls1 = low, or d1+, d1? ls0 = low and ls1=high; high impedance if ls0 = ls1 = low) sublvds out sublvds data link (active during normal operation when ls0 = low and ls1 = high, d2+, d2? high-impedance when ls1 = low) clk+, clk? sublvds output clock; clock polarity is fixed r0?r7 red pixel data (8); pin assignment depends on swap pin setting g0?g7 green pixel data (8); pin assignment depends on swap pin setting b0?b7 blue pixel data (8); pin assignment depends on swap pin setting hs horizontal sync vs vertical sync de data enable pclk input pixel clock; rising or falling clock polarity is selected by control input cpol ls0, ls1 link select (determines active sublvds data links and pll range) see table 2 cmos in disables the cmos drivers and turns off the pll, putting device in shutdown mode 1 ? transmitter enabled 0 ? transmitter disabled (shutdown) txen note: the txen input incorporates glitch-suppression logic to avoid device malfunction on short input spikes. it is necessary to pull txen high for longer than 10 m s to enable the transmitter. it is necessary to pull the txen input low for longer than 10 m s to disable the transmitter. at power up, the transmitter is enabled immediately if txen = 1 and disabled if txen = 0 input clock polarity selection cpol cmos in 0 ? rising edge clocking 1 ? falling edge clocking bus swap swaps the bus pins to allow device placement on top or bottom of pcb. see pinout drawing for pin assignments. swap cmos in 0 ? data input from b0...r7 1 ? data input from r7...b0 v dd supply voltage gnd supply ground v ddlvds sublvds i/o supply voltage gnd lvds sublvds ground power supply (1) v ddplla pll analog supply voltage gnd plla pll analog gnd v ddplld pll digital supply voltage gnd plld pll digital gnd (1) for a multilayer pcb, it is recommended to keep one common gnd layer underneath the device and connect all ground terminals directly to this plane. 5 submit documentation feedback www.ti.com
functional description serialization modes 1-channel mode 2-channel mode SN65LVDS301 slls681c ? february 2006 ? revised august 2006 the SN65LVDS301 transmitter has three modes of operation controlled by link-select pins ls0 and ls1. table 2 shows the serializer modes of operation. table 2. logic table: link select operating modes ls1 ls0 mode of operation data links status 0 0 1chm 1-channel mode (30-bit serialization rate) d0 active; d1, d2 high-impedance 0 1 2chm 2-channel mode (15-bit serialization rate) d0, d1 active; d2 high-impedance 1 0 3chm 3-channel mode (10-bit serialization rate) d0, d1, d2 active 1 1 reserved reserved while ls0 and ls1 are held low, the SN65LVDS301 transmits payload data over a single sublvds data pair, d0. the pll locks to pclk and internally multiplies the clock by a factor of 30. the internal high-speed clock is used to serialize (shift out) the data payload on d0. two reserved bits and the parity bit are added to the data frame. figure 3 illustrates the timing and the mapping of the data payload into the 30-bit frame. the internal high-speed clock is divided by a factor of 30 to recreate the pixel clock, and presented on the sublvds clk output. while in this mode, the pll can lock to a clock that is in the range of 4 mhz through 15 mhz. this mode is intended for smaller video display formats (e.g. qvga to hvga) that do not require the full bandwidth capabilities of the SN65LVDS301. figure 3. data and clock output in 1-channel mode (ls0 and ls1 = low). while ls0 is held high and ls1 is held low, the SN65LVDS301 transmits payload data over two sublvds data pairs, d0 and d1. the pll locks to pclk and internally multiplies it by a factor of 15. the internal high-speed clock is used to serialize the data payload on d0, and d1. two reserved bits and the parity bit are added to the data frame. figure 4 illustrates the timing and the mapping of the data payload into the 30-bit frame and how the frame becomes split into the two output channels. the internal high-speed clock is divided by 15 to recreate the pixel clock, and presented on sublvds clk. the pll can lock to a clock that is in the range of 8 mhz through 30 mhz in this mode. typical applications for using the 2-channel mode are hvga and vga displays. figure 4. data and clock output in 2-channel mode (ls0 = high; ls1 = low). 6 submit documentation feedback www.ti.com d0 +/C channel clk+ b7 b6 r7 r6 r5 r4 r3 r2 r1 r0 g7 g6 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 vs hs de 0 0 cp r7 r6 cp 0 0 clkC r7 r6 r5 r4 r3 r2 r1 r0 g7 g6 g5 g4 vs 0 cp 0 b7 b6 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 hs de 0 cp r7 r6 g3 g2 clk + clkC d0 +/C channel d1 +/C channel
3-channel mode powerdown modes shutdown mode standby mode SN65LVDS301 slls681c ? february 2006 ? revised august 2006 while ls0 is held low and ls1 is held high, the SN65LVDS301 transmits payload data over three sublvds data pairs d0, d1, and d2. the pll locks to pclk, and internally multiplies it by 10. the internal high-speed clock is used to serialize the data payload on d0, d1, and d2. two reserved bits and the parity bit are added to the data frame. figure 5 illustrates the timing and the mapping of the data payload into the 30-bit frame and how the frame becomes split over the three output channels. the internal high speed clock is divided back down by a factor of 10 to recreate the pixel clock and presented on sublvds clk output. while in this mode, the pll can lock to a clock in the range of 20 mhz through 65 mhz. the 3-channel mode supports applications with very large display resolutions such as vga or xga. figure 5. data and clock output in 3-channel mode (ls0 = low; ls1 = high). the SN65LVDS301 transmitter has two powerdown modes to facilitate efficient power management. the SN65LVDS301 enters shutdown mode when the txen pin is asserted low. this turns off all transmitter circuitry, including the cmos input, pll, serializer, and sublvds transmitter output stage. all outputs are high-impedance. current consumption in shutdown mode is nearly zero. the SN65LVDS301 enters the standby mode if txen is high and the pclk input signal frequency is less than 500khz. all circuitry except the pclk input monitor is shut down, and all outputs enter high-impedance mode. the current consumption in standby mode is very low. when the pclk input signal is completely stopped, the i dd current consumption is less than 10 m a. the pclk input must not be left floating. note: a floating (left open) cmos input allows leakage currents to flow from v dd to gnd. to prevent large leakage current, a cmos gate must be kept at a valid logic level, either v ih or v il . this can be achieved by applying an external voltage of v ih or v il to all SN65LVDS301 inputs. 7 submit documentation feedback www.ti.com d0 +/- channel clk + b7 b6 r7 r6 r5 r4 r3 r2 r1 r0 g7 g6 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 vs hs de cp 0 0 cp 0 0 clk - b7 b6 r7 r6 g7 g6 d1 +/- channeld2 +/- channel
active modes acquire mode (pll approaches lock) transmit mode parity bit generation status detect and operating modes flow diagram SN65LVDS301 slls681c ? february 2006 ? revised august 2006 when txen is high and the pclk input clock signal is faster than 3 mhz, the SN65LVDS301 enters active mode. current consumption in active mode depends on operating frequency and the number of data transitions in the data payload. the pll is enabled and attempts to lock to the input clock. all outputs remain in high-impedance mode. when the pll monitor detects stable pll operation, the device switches from acquire to transmit mode. for proper device operation, the pixel clock frequency must fall within the valid f pclk range specified under recommended operating conditions. if the pixel clock frequency is larger than 3 mhz but smaller than f pclk (min), the SN65LVDS301 pll is enabled. under such conditions, it is possible for the pll to lock temporarily to the pixel clock, causing the pll monitor to release the device into transmit mode. if this happens, the pll may or may not be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and pll deadlock (loss of vco oscillation). after the pll achieves lock, the device enters the normal transmit mode. the clk pin outputs a copy of pclk. based on the selected mode of operation, the d0, d1, and d2 outputs carry the serialized data. in 1-channel mode, outputs d1 and d2 remain high-impedance. in the 2-channel mode, output d2 remains high-impedance. the SN65LVDS301 transmitter calculates the parity of the transmit data word and sets the parity bit accordingly. the parity bit covers the 27 bit data payload consisting of 24 bits of pixel data plus vs, hs and de. the two reserved bits are not included in the parity generation. odd parity bit signaling is used. the transmitter sets the parity bit if the sum of the 27 data bits result in an even number of ones. the parity bit is cleared otherwise. this allows the receiver to verify parity and detect single bit errors. the SN65LVDS301 switches between the power saving and active modes in the following way: figure 6. status detect and operating modes flow diagram 8 submit documentation feedback www.ti.com standby mode transmit mode acquire mode txen high > 10 s m power up txen = 0 power up txen = 1 clk active pll achieved lock shutdown mode txen low > 10 s m txen low > 10 s m txen low > 10 s m pclk stops or lost pclk stops or lost pclk active power up txen = 1 clk inactive
SN65LVDS301 slls681c ? february 2006 ? revised august 2006 table 3. status detect and operating modes descriptions mode characteristics conditions shutdown mode least amount of power consumption (1) (most circuitry turned txen is low (1) (2) off); all outputs are high-impedance standby mode low power consumption (only clock activity circuit active; pll txen is high; pclk input signal is missing or is disabled to conserve power); all outputs are inactive (2) high-impedance acquire mode pll tries to achieve lock; all outputs are high-impedance txen is high; pclk input monitor detected input activity transmit mode data transfer (normal operation); transmitter serializes data txen is high and pll is locked to incoming clock and transmits data on serial output; unused outputs remain high-impedance (1) in shutdown mode, all SN65LVDS301 internal switching circuits (e.g., pll, serializer, etc.) are turned off to minimize power consumption. the input stage of any input pin remains active. (2) leaving inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. all inputs must be tied to a valid logic level v il or v ih during shutdown or standby mode. operating mode transitions mode transition use case transition specifics shutdown ? standby drive txen high to enable 1. txen high > 10 m s transmitter 2. transmitter enters standby mode a. all outputs are high-impedance b. transmitter turns on clock input monitor standby ? acquire transmitter activity detected 1. pclk input monitor detects clock input activity; 2. outputs remain high-impedance; 3. pll circuit is enabled acquire ? transmit link is ready to transfer data 1. pll is active and approaches lock 2. pll achieved lock within 2 ms 3. parallel data input latches into shift register 4. clk output turns on 5. selected data outputs turn on and send out first serial data bit transmit ? standby request transmitter to enter 1. pclk input monitor detects missing pclk standby mode by stopping 2. transmitter indicates standby, putting all outputs into high-impedance; pclk 3. pll shuts down; 4. pclk activity input monitor remains active transmit/standby ? turn off transmitter 1. txen pulled low for longer than 10us shutdown 2. transmitter indicates standby, putting output clk+ and clk? into high-impedance state; 3. transmitter puts all other outputs into high-impedance state 4. most ic circuitry is shut down for least power consumption 9 submit documentation feedback www.ti.com
absolute maximum ratings (1) dissipation ratings thermal characteristics SN65LVDS301 slls681c ? february 2006 ? revised august 2006 ordering information part number package shipping method SN65LVDS301zqe tray zqe SN65LVDS301zqer reel over operating free-air temperature range (unless otherwise noted) value unit supply voltage range, v dd (2) , v ddplla , v ddplld , v ddlvds -0.3 to 2.175 v voltage range at any input when v ddx > 0 v -0.5 to 2.175 v or output terminal when v ddx 0 v -0.5 to v dd + 2.175 v human body model (3) (all pins) 3 kv electrostatic discharge charged-device mode (4) l (all pins) 500 v machine model (5) (all pins) 200 continuous power dissipation see dissipation rating table (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to the gnd terminals. (3) in accordance with jedec standard 22, test method a114-a. (4) in accordance with jedec standard 22, test method c101. (5) in accordance with jedec standard 22, test method a115-a circuit derating factor (1) t a = 85 c package t a < 25 c board model above t a = 25 c power rating zqe low-k (2) 592 mw 7.407 mw/ c 148 mw (1) this is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. (2) in accordance with the low-k thermal metric definitions of eia/jesd51-2. parameter test conditions value unit pclk at 4 mhz 14.4 typical v ddx = 1.8 v, t a = 25 c mw pclk at 65 mhz 44.5 p d device power dissipation pclk at 4 mhz 22.3 maximum v ddx = 1.95 v, t a = ?40 c mw pclk=65 mhz 71.8 10 submit documentation feedback www.ti.com
recommended operating conditions (1) SN65LVDS301 slls681c ? february 2006 ? revised august 2006 min nom max unit v dd supply voltages 1.65 1.8 1.95 v v ddplla v ddplld v ddlvds v ddn(pp) test set-up see figure 12 supply voltage noise f(pclk) 50 mhz; f(noise) = 1 hz to 2 ghz 100 magnitude 50 mhz (all mv f(pclk) > 50 mhz; f(noise) = 1 hz to 1 mhz 100 supplies) f(pclk) > 50 mhz; f(noise) > 1 mhz 40 1-channel transmit mode, see figure 3 4 15 2-channel transmit mode, see figure 4 8 30 f pclk pixel clock frequency mhz 3-channel transmit mode, see figure 5 20 65 frequency threshold standby mode to active 0.5 3 mode (2) , see figure 16 t h x f pclk pclk input duty cycle 0.33 0.67 t a operating free-air ?40 85 c temperature t jit(per)pclk pclk rms period jitter (3) 5 ps-rms t jit(tj)pclk pclk total jitter 0.05/f pclk s measured on pclk input t jit(cc)pclk pclk peak 0.02/f pclk s cycle-to-cycle jitter (4) pclk, r[0:7], g[0:7], b[0:7], vs, hs, de, pclk, ls[1:0], cpol, txen, swap v ih high-level input voltage 0.7 v dd v dd v v il low-level input voltage 0.3 v dd v t ds data set up time prior to 2.0 ns pclk transition f (pclk) = 65 mhz; see figure 8 t dh data hold time after pclk 2.0 ns transition (1) unused single-ended inputs must be held high or low to prevent them from floating. (2) pclk input frequencies lower than 500 khz force the SN65LVDS301into standby mode. input frequencies between 500 khz and 3 mhz may or may not activate the SN65LVDS301. input frequencies beyond 3 mhz activate the SN65LVDS301. (3) period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles. (4) cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles; over a random sample of 1,000 adjacent cycle pairs. 11 submit documentation feedback www.ti.com
device electrical characteristics output electrical characteristics SN65LVDS301 slls681c ? february 2006 ? revised august 2006 over recommended operating conditions (unless otherwise noted) param test conditions min typ (1) max unit eter v dd =v ddplla =v ddplld =v ddlvds , f pclk = 4 mhz 9.0 11.4 r l(pclk) =r l(d0) =100 w , v ih =v dd , v il =0 v, f pclk = 6 mhz 10.6 12.6 ma txen at v dd , f pclk = 15 mhz 16 18.8 alternating 1010 serial bit pattern 1chm v dd =v ddplla =v ddplld =v ddlvds , f pclk = 4 mhz 8.0 r l(pclk) =r l(d0) =100 w , v ih =v dd , v il =0 v, f pclk = 6 mhz 8.9 ma txen at v dd , f pclk = 15 mhz 14.0 typical power test pattern (see table 5 ) v dd =v ddplla =v ddplld =v ddlvds , f pclk = 8 mhz 13.7 15.9 r l(pclk) =r l(d0) =100 w , v ih =v dd , v il =0 v, f pclk = 22 mhz 18.4 22.0 ma txen at v dd , f pclk = 30 mhz 21.4 25.8 alternating 1010 serial bit pattern; 2chm v dd =v ddplla =v ddplld =v ddlvds , f pclk = 8 mhz 11.5 r l(pclk) =r l(d0) =100 w , v ih =v dd , v il =0 v, f pclk = 22 mhz 16.0 ma txen at v dd , i dd f pclk = 30 mhz 19.1 typical power test pattern (see table 6 ) v dd =v ddplla =v ddplld =v ddlvds , f pclk = 20 mhz 20.0 22.5 r l(pclk) =r l(d0) =100 w , v ih =v dd , v il =0 v, f pclk = 65 mhz ma txen at v dd , 29.1 36.8 alternating 1010 serial bit pattern 3chm v dd =v ddplla =v ddplld =v ddlvds , f pclk = 20 mhz 15.9 r l(pclk) =r l(d0) =100 w , v ih =v dd , v il =0 v, f pclk = 65 mhz ma txen at v dd , 24.7 typical power test pattern (see table 7 ) standby mode v dd = v ddplla = v ddplld 0.61 10 m a = v ddlvds , r l(pclk) =r l(d0) =100 w , v ih =v dd , v il =0 v, all shutdown mode 0.55 10 m a inputs held static high or static low (1) all typical values are at 25 c and with 1.8 v supply unless otherwise noted. over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ (1) max unit sublvds output (d0+, d0?, d1+, d1?, d2+, d1?, clk+, and clk?) v oc(ss)m steady-state common-mode output voltage output load see figure 10 0.8 0.9 1.0 v v ocm(ss) change in steady-state common-mode output voltage ?10 10 mv v ocm(pp) peak-to-peak common mode output voltage 75 mv |v od | differential output voltage magnitude 100 150 200 mv |v dx+ ? v dx? |, |v clk+ ? v clk? | d |v od | change in differential output voltage between logic states ?10 10 mv z od(clk) differential small-signal output impedance txen at v dd 210 w i osd differential short-circuit output current v od = 0 v, f pclk = 28 mhz 10 ma i os short circuit output current (2) v o = 0 v or v dd 5 i oz high-impedance state output current v o = 0 v or v dd (max), ?3 3 m a txen at gnd (1) all typical values are at 25 c and with 1.8 v supply unless otherwise noted. (2) all SN65LVDS301 outputs tolerate shorts to gnd or v dd without permanent device damage. 12 submit documentation feedback www.ti.com
input electrical characteristics switching characteristics SN65LVDS301 slls681c ? february 2006 ? revised august 2006 over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ (1) max unit pclk, r[0:7], g[0:7], b[0:7], vs, hs, de, pclk, ls[1:0], cpol, txen, swap i ih high-level input current v in = 0.7 v dd ?200 200 na i il low-level input current v in = 0.3 v dd ?200 200 c in input capacitance 1.5 pf (1) all typical values are at 25 c and with 1.8 v supply unless otherwise noted. over recommended operating conditions (unless otherwise noted) parameter test conditions min typ (1) max unit t r 20%-to-80% differential see figure 9 and figure 10 250 500 output signal rise time ps t f 20%-to-80% differential see figure 9 and figure 10 250 500 output signal fall time tested from pclk input to f pclk = 22 mhz 0.082 f pclk pll bandwidth (3db cutoff f bw mhz clk output, see figure 7 (2) frequency) f pclk = 65 mhz 0.07 f pclk t pd(l) propagation delay time, txen at v dd , v ih =v dd , 1-channel mode 0.8/f pclk 1/f pclk 1.2/f pclk input to serial output (data v il =gnd, r l =100 w 2-channel mode 1.0/f pclk 1.21/f pclk 1.5/f pclk s latency figure 11 ) 3-channel mode 1.1/f pclk 1.31/f pclk 1.6/f pclk t h f clk0 output clk duty cycle 1-channel and 3-channel 0.45 0.50 0.55 mode 2-channel mode 0.49 0.53 0.58 t gs txen glitch suppression v ih =v dd , v il =gnd, txen toggles between v il and v ih , 3.8 10 m s pulse width (3) see figure 14 and figure 15 t pwrup enable time from power time from txen pulled high to clk and dx outputs 0.24 2 ms down ( - txen) enabled and transmit valid data; see figure 15 t pwrdn disable time from active txen is pulled low during transmit mode; time 0.5 11 mode ( txen) measurement until output is disabled and pll is m s shutdown; see figure 15 t wakup enable time from standby txen at v dd ; device in standby; time measurement from 0.23 2 ( ? pclk) pclk starts switching to clk and dx outputs enabled and ms transmit valid data; see figure 15 t sleep disable time from active txen at v dd ; device is transmitting; time measurement 0.4 100 mode (pclk stopping) from pclk input signal stops until clk + dx outputs are m s disabled and pll is disabled; see figure 15 (1) all typical values are at 25 c and with 1.8 v supply unless otherwise noted. (2) the maximum limit is based on statistical analysis of the device performance over process, voltage, and temp ranges. this parameter is functionality tested only on automatic test equipment (ate). (3) the txen input incorporates glitch-suppression circuitry to disregard short input pulses. t gs is the duration of either a high-to-low or low-to-high transition that is suppressed. 13 submit documentation feedback www.ti.com
timing characteristics SN65LVDS301 slls681c ? february 2006 ? revised august 2006 figure 7. lvds301 pll bandwidth (also showing the lvds302 pll bandwidth) parameter test conditions min typ max unit 1chm: x=0..29, f pclk =15 mhz; txen at v dd , v ih =v dd , v il =gnd, r l =100 w , test pattern as in table 10 (3) 1chm: x=0..29, f pclk =4 mhz to 15 mhz (4) 2chm: x = 0..14, f pclk = 30 mhz txen at v dd , v ih =v dd , v il =gnd, output pulse position, r l =100 w , test pattern as in table 11 (3) t pposx serial data to - clk; see ps 2chm: x=0..14, (1) (2) and figure 13 f pclk = 8 mhz to 30 mhz (4) 3chm: x=0..9, f pclk =65 mhz, txen at v dd , v ih =v dd , v il =gnd, r l =100 w , test pattern as in table 12 (3) 3chm: x=0..9, f pclk =20 mhz to 65 mhz (4) (1) this number also includes the high-frequency random and deterministic pll clock jitter that is not traceable by the sn65lvds302 receiver pll; tpposx represents the total timing uncertainty of the transmitter necessary to calculate the jitter budget when combined with the sn65lvds302 receiver; (2) the pulse position min/max variation is given with a bit error rate target of 10 ?12 ; the measurement estimates the random jitter contribution to the total jitter contribution by multiplying the random rms jitter by the factor 14; measurements of the total jitter are taken over a sample amount of > 10 ?12 samples. (3) the minimum and maximum limits are based on statistical analysis of the device performance over process, voltage, and temp ranges. this parameter is functionality tested only on automatic test equipment (ate). (4) these minimum and maximum limits are simulated only. 14 submit documentation feedback www.ti.com pll frequency ? mhz 4.0% 5.0% 6.0% 7.0% 8.0% 9.0% 10.0% 11.0% 12.0% 0 100 200 300 400 500 600 700 pll bw [% of pclk frequency] 9% 8.5% 7% 7.5% rx pll bw tx pll bw 0 40 50 60 70 10 20 30 pclk frequency - mhz pll bandwidth - % 6.0 6.5 7.0 7.5 8.0 8.5 9.0 65 mhz: 7.0% 4 mhz: 8.5% 15 mhz: 7.6% spec limit 3chm 30 mhz: 7.6% spec limit 2chm spec limit 1chm 8 mhz: 8.5% 20 mhz: 8.3% ps 330 f 30 x pclk - ps 330 f 30 x pclk + pclk x C 0.1845 f 30 pclk f 30 x 0.1845 + ps 330 f 15 x pclk - ps 330 f 15 x pclk + pclk x C 0.1845 f 15 pclk x + 0.1845 f 15 ps 210 f 10 x pclk - ps 210 f 10 x pclk + pclk f 10 x 0.153 - pclk f 10 x 0.153 +
parameter measurement information SN65LVDS301 slls681c ? february 2006 ? revised august 2006 figure 8. setup/hold time figure 9. rise and fall time definitions figure 10. driver output voltage test circuit and definitions 15 submit documentation feedback www.ti.com r[7:0], g[7:0], b[7:0]; vs, hs, de, ls0, ls1, txen, swap, cpol pclk (cpol=low) t ds t dh t r v ih v il v ih v il 0 v 20% 80% 150mv (nom)?150mv (nom) t f t r v od SN65LVDS301 clk?, dx? clk+, dx+ 975mv (nom)825mv (nom) r1 = 49.9 r2 = 49.9 c2 = 1 pf c1 = 1 pf v od v dx+ or v clk+ v dx? or v clk? v ocm v ocm v ocm (pp) v ocm (ss) notes: a. 20 mhz output test pattern on all differental outputs (clk, d0, d1, and d2): this is achieved by: 1. device is set to 3-channel-mode; 2. f pclk = 20 mhz 3. inputs r[7:3] = b[7:3] connected to v , all other data inputs set to gnd. dd b. c1, c2 and c3 includes instrumentation and fixture capacitance; tolerance 20%; c, r1 and r2 tolerance 1%. c. the measurement of v ocm (pp) and v oc (ss) are taken with test equipment bandwidth >1 ghz.
SN65LVDS301 slls681c ? february 2006 ? revised august 2006 parameter measurement information (continued) figure 11. t pd(l) propagation delay input to output (ls0 = ls1 = 0; cpol = 0) figure 12. power supply noise test set-up figure 13. t sk(0) sublvds output pulse position measurement 16 submit documentation feedback www.ti.com r6 (n) r7 (n?1) r7 r6 r7 d0+ clk+ clk? cmos data in pclk r6 cp cp pixel (n) pixel (n+1) r7 (n) r7 (n+1) r6 (n+1) r6 (n?1) t prop v dd /2 r6 (n?1) r7 (n?1) pixel (n?2) pixel (n?1) r6 (n) r7 (n) note: the generator regulates the noise amplitude at point to the target amplitude given under the table recommended operating conditions noise generator 100 mv SN65LVDS301 v ddplla 1.8 v supply v ddplld v dd v ddlvds gnd 1.6 h 10 f m 2 1 1 1 clk+ bit 0 bit1 bit2 bitx bit0 bit1 note:1?channel mode: x=0..29; m=0 2?channel mode: x=0..14; m=1 3?channel mode: x=0....9; m=2 clk? t clk+ current cycle next cycle t ppos0 t ppos1 t ppos2 t pposx d[0:m]
SN65LVDS301 slls681c ? february 2006 ? revised august 2006 parameter measurement information (continued) figure 14. transmitter behavior while approaching sync figure 15. transmitter enable glitch suppression time figure 16. standby detection 17 submit documentation feedback www.ti.com txen pclk clk d0, d1, d2 t gs v dd /2 pll approaches lock t pwrup vco internal signal clk+ pclk t wakeup t sleep transmitter disabled (off) transmitter aquires lock, outputs still disabled transmitter enabled, output data valid transmitter enabled, output data valid transmitter disabled (off)
power consumption tests SN65LVDS301 slls681c ? february 2006 ? revised august 2006 parameter measurement information (continued) table 4 shows an example test pattern word. table 4. example test pattern word word r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0x7c3e1e7 7 c 3 e 1 e 7 r7 r6 r5 r4 r3 r2 r1 r0 g7 g6 g5 g4 g3 g2 g1 g0 b7 b6 b5 b4 b3 b2 b1 b0 0 vs hs de 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 typical ic power consumption test pattern the typical power consumption test patterns consists of sixteen 30-bit transmit words in 1-channel mode, eight 30-bit transmit words in 2-channel mode and five 30-bit transmit words in 3-channel mode. the pattern repeats itself throughout the entire measurement. it is assumed that every possible transmit code on rgb inputs has the same probability to occur during typical device operation. table 5. typical ic power consumption test pattern, 1-channel mode word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0x0000007 2 0xfff0007 3 0x01fff47 4 0xf0e07f7 5 0x7c3e1e7 6 0xe707c37 7 0xe1ce6c7 8 0xf1b9237 9 0x91bb347 10 0xd4ccc67 11 0xad53377 12 0xacb2207 13 0xaab2697 14 0x5556957 15 0xaaaaab3 16 0xaaaaaa5 18 submit documentation feedback www.ti.com
maximum power consumption test pattern SN65LVDS301 slls681c ? february 2006 ? revised august 2006 table 6. typical ic power consumption test pattern, 2-channel mode word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0x0000001 2 0x03f03f1 3 0xbffbff1 4 0x1d71d71 5 0x4c74c71 6 0xc45c451 7 0xa3aa3a5 8 0x5555553 table 7. typical ic power consumption test pattern, 3-channel mode word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0xffffff1 2 0x0000001 3 0xf0f0f01 4 0xcccccc1 5 0xaaaaaa7 the maximum (or worst-case) power consumption of the SN65LVDS301 is tested using the two different test patterns shown in table 8 and table 9 . the test patterns consist of sixteen 30-bit transmit words in 1-channel mode, eight 30-bit transmit words in 2-channel mode and five 30-bit transmit words in 3-channel mode. the pattern repeats itself throughout the entire measurement. it is assumed that every possible transmit code on rgb inputs has the same probability to occur during typical device operation. table 8. worst-case power consumption test pattern word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0xaaaaaa5 2 0x5555555 table 9. worst-case power consumption test pattern word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0x0000000 2 0xffffff7 19 submit documentation feedback www.ti.com
output skew pulse position & jitter performance SN65LVDS301 slls681c ? february 2006 ? revised august 2006 the following test patterns are used to measure the output-skew pulse position and the jitter performance of the SN65LVDS301. the jitter test pattern stresses the interconnect, particularly to test for isi. very long run-lengths of consecutive bits incorporate very high and low data rates, maximinges switching noise. each pattern is self-repeating for the duration of the test. table 10. transmit jitter test pattern, 1-channel mode word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0x0000001 2 0x0000031 3 0x00000f1 4 0x00003f1 5 0x0000ff1 6 0x0003ff1 7 0x000fff1 8 0x0f0f0f1 9 0x0c30c31 10 0x0842111 11 0x1c71c71 12 0x18c6311 13 0x1111111 14 0x3333331 15 0x2452413 16 0x22a2a25 17 0x5555553 18 0xdb6db65 19 0xcccccc1 20 0xeeeeee1 21 0xe739ce1 22 0xe38e381 23 0xf7bdee1 24 0xf3cf3c1 25 0xf0f0f01 26 0xfff0001 27 0xfffc001 28 0xffff001 29 0xffffc01 30 0xfffff01 31 0xfffffc1 32 0xffffff1 20 submit documentation feedback www.ti.com
SN65LVDS301 slls681c ? february 2006 ? revised august 2006 table 11. transmit jitter test pattern, 2-channel mode word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0x0000001 2 0x000fff3 3 0x8008001 4 0x0030037 5 0xe00e001 6 0x00ff001 7 0x007e001 8 0x003c001 9 0x0018001 10 0x1c7e381 11 0x3333331 12 0x555aaa5 13 0x6dbdb61 14 0x7777771 15 0x555aaa3 16 0xaaaaaa5 17 0x5555553 18 0xaaa5555 19 0x8888881 20 0x9242491 21 0xaaa5571 22 0xcccccc1 23 0xe3e1c71 24 0xffe7ff1 25 0xffc3ff1 26 0xff81ff1 27 0xfe00ff1 28 0x1ff1ff1 29 0xffcffc3 30 0x7ff7ff1 31 0xfff0007 32 0xffffff1 21 submit documentation feedback www.ti.com
SN65LVDS301 slls681c ? february 2006 ? revised august 2006 table 12. transmit jitter test pattern, 3-channel mode word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0x0000001 2 0x0000001 3 0x0000003 4 0x0101013 5 0x0303033 6 0x0707073 7 0x1818183 8 0xe7e7e71 9 0x3535351 10 0x0202021 11 0x5454543 12 0xa5a5a51 13 0xadadad1 14 0x5555551 15 0xa6a2aa3 16 0xa6a2aa5 17 0x5555553 18 0x5555555 19 0xaaaaaa1 20 0x5252521 21 0x5a5a5a1 22 0xababab1 23 0xfdfcfd1 24 0xcaaaca1 25 0x1818181 26 0xe7e7e71 27 0xf8f8f81 28 0xfcfcfc1 29 0xfefefe1 30 0xffffff1 31 0xffffff5 32 0xffffff5 22 submit documentation feedback www.ti.com
typical characteristics SN65LVDS301 slls681c ? february 2006 ? revised august 2006 powerdown, standby supply current vs temperature supply current i dd vs temperature figure 17. figure 18. supply current vs pclk frequency differential output swing vs pclk frequency figure 19. figure 20. cycle-to-cycle output jitter pll bandwidth vs pclk frequency figure 21. figure 22. 23 submit documentation feedback www.ti.com 0.1 1.0 -50 -30 -10 10 30 50 70 90 temperature - c iddq - a m power-down current standby current 0 20 -50 -30 -10 10 30 50 70 90 temperature - c idd - ma 5 10 15 2-channel mode, 11 mhz (hvga) 2-channel mode, 22 mhz (vga) 5 10 15 20 25 30 0 40 50 60 70 10 20 30 frequency - mhz idd - ma 1-channel mode 2-channel mode 3-channel mode 0 40 50 60 70 10 20 30 frequency - mhz 100 110 120 130 140 150 160 170 180 190 200 differential output swing vod - mv C40c 25c 85c 0 40 50 60 70 10 20 30 frequency - mhz 0 100 200 300 400 500 cc jitter - ps 2-channel mode 1-channel mode 3-channel mode
SN65LVDS301 slls681c ? february 2006 ? revised august 2006 typical characteristics (continued) cycle-to-cycle output jitter vs temperature output pulse position vs temperature figure 23. figure 24. data eye pattern, 2-channel mode data eye pattern, 3-channel mode figure 25. figure 26. qvga output waveform vga 2-channel output waveform figure 27. figure 28. 24 submit documentation feedback www.ti.com -50 -25 0 25 50 75 100 0 20 40 60 80 100 120 output pulse position (t ) - ps ppos 2-channel mode, 22 mhz (hvga) 2-channel mode, 11 mhz (vga) temperature - c -50 -25 0 25 50 75 100 temperature - c 0 50 100 150 200 cc jitter - ps 2-channel mode,f(pclk) = 22 mhz 2-channel mode, f(pclk) = 11 mhz C251 C190 0 190 249 response over 80-inch of fr-4 + 1m coax cable 1 ns/div 1-channel mode, f(pclk) = 5.5 mhz output voltage amplitude - mv C250 C190 0 190 250 response over 8-inch fr-4 + 1m coax cable 500 ps/div 2-channel mode, f(pclk) = 22 mhz output voltage amplitude - mv
SN65LVDS301 slls681c ? february 2006 ? revised august 2006 typical characteristics (continued) vga 2-channel output waveform vga3-channel output waveform figure 29. figure 30. xga 3-channel output waveform on the xga 3-channel output waveform sn65lvds302 when driven by the SN65LVDS301 figure 31. figure 32. pll phase noise output return loss figure 33. figure 34. 25 submit documentation feedback www.ti.com C251 C190 0 190 249 response over 80-inch fr-4 + 1m coax cable 500 ps/div 2-channel mode, f(pclk) = 22 mhz output voltage amplitude - mv C251 C190 0 190 249 output voltage amplitude - mv response over 80-inch fr-4 + 1m coax cable 1 ns/div 3-channel mode, f(pclk) = 22 mhz C251 C190 0 190 249 output voltage amplitude - mv response over 80-inch fr-4 + 1m coax cable 300 ps/div 3-channel mode, f(pclk) = 56 mhz output voltage amplitude - mv 400 mv/div response with 10-pf load 3.5 ns/div 3-channel mode, f(pclk) = 56 mhz f(pclk) = 65 mhz -50-60 -70 -80 -90 -100 -110 -120-130 -140 -150 -160 -170 -180 1 10 100 1k 10k 100k 1m 10m dbc/hz frequency - hz
SN65LVDS301 slls681c ? february 2006 ? revised august 2006 typical characteristics (continued) output common mode noise rejection crosstalk figure 35. figure 36. gtem sae j1752/3 emi test (a) figure 37. a. figure 37 shows a superimposed image of three emi measurements with the device operating at f(pclk) = 5 mhz, f(pclk) = 22 mhz, and f(pclk) = 65 mhz. this excellent emi performance meets the system requirements of dense, mobile designs with a noise floor of ~2 dbv (-105 dbm) and all spurs being smaller than 16 dbv (-101 dbm). the test was performed in compliance with the sae j1752/3 emi test guidelines. 26 submit documentation feedback www.ti.com
application information preventing increased leakage currents in control inputs power supply design recommendation decoupling recommendation vga application SN65LVDS301 slls681c ? february 2006 ? revised august 2006 a floating (left open) cmos input allows leakage currents to flow from v dd to gnd. do not leave any cmos input unconnected or floating. every input must be connected to a valid logic level v ih or v ol while power is supplied to v dd . this also minimizes the power consumption of standby and power down mode. for a multilayer pcb, it is recommended to keep one common gnd layer underneath the device and connect all ground terminals directly to this plane. the SN65LVDS301 was designed to operate reliably in a constricted environment with other digital switching ics. in cell phone designs, the SN65LVDS301 often shares a power supply with the application processor. the SN65LVDS301 can operate with power supply noise as specified in recommend device operating conditions. to minimize the power supply noise floor, provide good decoupling near the SN65LVDS301 power pins. the use of four ceramic capacitors (2 0.01 m f and 2 0.1 m f) provides good performance. at the very least, it is recommended to install one 0.1 m f and one 0.01 m f capacitor near the SN65LVDS301. to avoid large current loops and trace inductance, the trace length between decoupling capacitor and ic power inputs pins must be minimized. placing the capacitor underneath the SN65LVDS301 on the bottom of the pcb is often a good choice. figure 38 shows a possible implementation of a vga display. the lvds301 interfaces to the sn65lvds302, which is the corresponding receiver device to deserialize the data and drive the display driver. the pixel clock rate of 22 mhz assumes ~10% blanking overhead and 60 hz display refresh rate. the application assumes 24-bit color resolution. it is also shown, how the application processor provides a powerdown (reset) signal for both serializer and the display driver. the signal count over the fpc could be further decreased by using the standby option on the sn65lvds302 and pulling rxen high with a 30 k w resistor to v dd . figure 38. typical vga display application 27 submit documentation feedback www.ti.com spi reset 22mhz 27 pclk r[7:0] g[7:0] b[7:0] hs,vs,de d[7:0] d[15:8] d[23:16] hs,vs,de pixel clk vddx gnd 2x0.01uf 2x0.1uf ls0 ls1 txen 1.8v vddx gnd 2x0.01uf 2x0.1uf ls0 ls1 rxen 1.8v d0+ d0- clk+ clk- d1+ d1- d0+ d0- clk+ clk- d1+ d1- gnd 1.8v 2.7v gnd 1.8v 2.7v gnd gnd lcd with vga resolution 22mhz 27 pclk r[7:0] g[7:0] b[7:0] hs,vs,de spi serial port interface (3-wire if) 3 application processor (e.g. omap) SN65LVDS301 sn65lvds302 video mode display driver fpc 22mhz 330mbps 330mbps enable if fpc wire count is critical , replace this connection with a pull -up resistor at rxen
dual lcd-display application typical application frequencies SN65LVDS301 slls681c ? february 2006 ? revised august 2006 application information (continued) the example in figure 39 shows a possible application setup driving two video mode displays from one application processor. the data rate of 330 mbps at a pixel clock rate of 5.5 mhz corresponds to qvga resolution at 60 hz refresh rate and 10% blanking overhead. figure 39. example dual-qvga display application the SN65LVDS301 supports pixel clock frequencies from 4 mhz to 65 mhz over 1, 2, or 3 data lanes. table 13 provides a few typical display resolution examples and shows the number of data lanes necessary to connect the lvds301 with the display. the blanking overhead is assumed to be 20%. often, blanking overhead is smaller, resulting in a lower data rate. furthermore, the examples in the table assumes a display frame refresh rate of 60 hz or 90 hz. the actual refresh rate may differ depending on the application-processor clock implementation. table 13. typical application data rates & serial lane usage display screen visible blanking display pixel clock frequency serial data rate per lane resolution pixel count overhead refresh [mhz] 1-chm 2-chm 3-chm rate 176x220 (qcif+) 38,720 20% 90 hz 4.2 mhz 125 mbps 240x320 (qvga) 76,800 60 hz 5.5 mhz 166 mbps 640x200 128,000 9.2 mhz 276 mbps 138 mbps 352x416 (cif+) 146,432 10.5 mhz 316 mbps 158 mbps 352x440 154,880 11.2 mhz 335 mbps 167 mbps 320x480 (hvga) 153,600 11.1 mhz 332 mbps 166 mbps 800x250 200,000 14.4 mhz 432 mbps 216 mbps 640x320 204,800 14.7 mhz 442 mbps 221 mbps 640x480 (vga) 307,200 22.1 mhz 332 mbps 221 mbps 1024x320 327,680 23.6 mhz 354 mbps 236 mbps 854x480 (wvga) 409,920 29.5 mhz 443 mbps 295 mbps 800x600 (svga) 480,000 34.6 mhz 346 mbps 1024x768 (xga) 786,432 56.6 mhz 566 mbps 28 submit documentation feedback www.ti.com sclk 5.5mhz 18+3 pclk r[5:0] g[5:0] b[5:0] hs,vs,de d[5:0] d[11:6] d[17:12] hs,vs,de pixel clk vddx gnd 2x0.01uf 2x0.1uf vddx gnd 2x0.01uf 2x0.1uf rxen d0+ d0- clk+ clk- d0+ d0- clk+ clk- gnd 1.8v 2.7v gnd 1.8v 2.7v gnd gnd lcd with qvga resolution 21 r[5:0] g[5:0] b[5:0] hs,vs,de sclk application processor (e.g. omap) SN65LVDS301 sn65lvds302 display driver2 fpc 5.5mhz 330mbps sin lcd with qvga resolution display driver1 1.8v ls0 ls1 txen 1.8v ls0 ls1 sin sout sel2 sel1 sout en sclk sout ensin pclk pclk pclk
calculation example: hvga display SN65LVDS301 slls681c ? february 2006 ? revised august 2006 this example calculation shows a typical half-vga display with these parameters: display resolution: 480 x 320 frame refresh rate: 58.4 hz horizontal visible pixel: 480 columns horizontal front porch: 20 columns horizontal sync: 5 columns horizontal back porch: 3 columns vertical visible pixel: 320 lines vertical front porch: 10 lines vertical sync: 5 lines vertical back porch: 3 lines figure 40. hvga display parameters calculation of the total number of pixel and blanking overhead: visible area pixel count: 480 320 = 153600 pixel total frame pixel count: (480+20+5+3) (320+10+5+3) = 171704 pixel blanking overhead: (171704-153600) ? 153600 = 11.8 % the application requires following serial-link parameters: pixel clk frequency: 171704 58.4 hz = 10.0 mhz serial data rate: 1-channel mode: 10.0 mhz 30 bit/channel = 300 mbps 2-channel mode: 10.0 mhz 15 bit/channel = 150 mbps 29 submit documentation feedback www.ti.com visible area = 480 column visible area entire display vsync = 5 vbp = 3 visible area = 320 lines vfp = 10 hsync = 5 hfp = 20 hbp
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) SN65LVDS301zqe active bga mi crosta r juni or zqe 80 360 green (rohs & no sb/br) snagcu level-3-260c-168 hr SN65LVDS301zqer active bga mi crosta r juni or zqe 80 2500 green (rohs & no sb/br) snagcu level-3-260c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 12-sep-2006 addendum-page 1
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant SN65LVDS301zqer bga mi crosta r juni or zqe 80 2500 330.0 12.4 5.3 5.3 1.5 8.0 12.0 q1 package materials information www.ti.com 19-mar-2008 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) SN65LVDS301zqer bga microstar junior zqe 80 2500 340.5 333.0 20.6 package materials information www.ti.com 19-mar-2008 pack materials-page 2

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